The present invention relates to an image signal processing device. More particularly, this invention relates to an image signal processing device which implements coding/decoding in high speed in an arithmetic coding used under Recommendation T.82 and T.85 of ITU-T.
Formerly, in general, an image signal processing device is constituted as a device which works according to an arithmetic coding. In recent years, in the arithmetic coding, a coding system of static image in Recommendation T.82 and T.85 of ITU-T (International Telecommunication Union) is applied thereto to be used. This arithmetic coding system implements coding in such a way that the coding system predicts an occurrence pixel in every one pixel unit. In order to predict a pixel, a set of peripheral pixels called a model template is used as a reference pixel. Such a combination of the peripheral pixels is called a context. Each context represents status of the peripheral pixels. Thus, each context has a pixel value which is easy to occur or with an occurrence probability or so forth. The image signal processing device implements coding/decoding processing of the pixel while using this information.
FIG. 1 is a coding flowchart of an arithmetic coding. In FIG. 1, firstly, initialization of respective parameters is implemented (STEP S100), subsequently, read-in operation of a pixel to come to coding candidate (hereinafter referred to as xe2x80x98PIXxe2x80x99) and a context (hereinafter referred to as xe2x80x98CXxe2x80x99) corresponding to the xe2x80x98PIXxe2x80x99 are implemented (S101). Coding processing of xe2x80x98PIXxe2x80x99 is implemented using read-in xe2x80x98PIXxe2x80x99 and xe2x80x98CXxe2x80x99 (S102).
Above-described processing of STEP S101, and STEP S102 are continued up to end of stripe operation (S103). Here, the stripe is processing unit of coding. In general, the coding processing is performed while dividing one page of image into some stripes. When one stripe ends, xe2x80x98FLUSHxe2x80x99 processing is performed for expelling codes from inside of register and/or buffer (S104).
FIG. 2 is a detailed flowchart of xe2x80x98coding processingxe2x80x99 of STEP S102 of FIG. 1. In FIG. 2, xe2x80x98PIXxe2x80x99 is a present coding candidate pixel value, and xe2x80x98MPS [CX]xe2x80x99 is value of more probability symbol (in other word, superior probability symbol, hereinafter, referred to as xe2x80x98MPSxe2x80x99) of context xe2x80x98CXxe2x80x99 on that occasion. The present coding candidate pixel value xe2x80x98PIXxe2x80x99 is compared with the more probability symbol of context xe2x80x98CXxe2x80x99 on that occasion xe2x80x98MPS[CX]xe2x80x99 (STEP S200), before, discriminating whether the present coding candidate pixel value xe2x80x98PIXxe2x80x99 is more probability symbol xe2x80x98MPSxe2x80x99 (STEP S200/Yes) or the present coding candidate pixel value xe2x80x98PIXxe2x80x99 is less probability symbol (in other word, inferior probability symbol, hereinafter, referred to as LPS) (STEP S200/No).
When the present candidate pixel value xe2x80x98PIXxe2x80x99 is the less probability symbol xe2x80x98LPSxe2x80x99, subtraction is performed between value of xe2x80x98Axe2x80x99-register which indicates a xe2x80x98probability area widthxe2x80x99, and value of occurrence probability of the less probability symbol xe2x80x98LPSxe2x80x99 (hereinafter referred to as xe2x80x98LSZxe2x80x99), subsequently, result of the subtraction is substituted (STEP S201). Next, the value of the xe2x80x98Axe2x80x99-register calculated earlier is compared with xe2x80x98LSZxe2x80x99 (STEP S202). When the result of the comparison is xe2x80x98Axe2x80x99xe2x89xa7xe2x80x98LSZxe2x80x99, addition is performed between value of xe2x80x98Cxe2x80x99-register to be an operation register and value of xe2x80x98Axe2x80x99-register, subsequently, xe2x80x98LSZxe2x80x99 is substituted into the xe2x80x98Axe2x80x99-register (STEP S203).
When the result of the comparison of STEP S202 is xe2x80x98Axe2x80x99 less than xe2x80x98LSZxe2x80x99, or xe2x80x98Axe2x80x99xe2x89xa7xe2x80x98LSZxe2x80x99, after termination of STEP S203, value of xe2x80x98SWTCHxe2x80x99 is checked, in the case of xe2x80x98SWTCHxe2x80x99=1, value of xe2x80x98MPSxe2x80x99 is inverted (STEP S204/Yes, STEP S205). When the xe2x80x98SWTCHxe2x80x99 is xe2x80x98SWTCHxe2x80x99=0 (STEP S204/No), nothing is performed and going to next STEP S206.
Finally, xe2x80x98NLPS[ST[CX]]xe2x80x99 representing status of next objective of transition at the time of xe2x80x98LPSxe2x80x99 is substituted into value xe2x80x98ST[CX]xe2x80x99 of status (hereinafter, referred to as xe2x80x98STxe2x80x99) representing probability transition state of xe2x80x98CXxe2x80x99. Subsequently, normalization processing is implemented (STEP S206), to terminate coding processing of the xe2x80x98PIXxe2x80x99.
A probability transition table is constituted by value of xe2x80x98LSZxe2x80x99, xe2x80x98NLPSxe2x80x99 to be next objective of transition when xe2x80x98PIXxe2x80x99 is xe2x80x98LPSxe2x80x99, xe2x80x98NMPSxe2x80x99 to be next objective of transition in case of xe2x80x98MPSxe2x80x99, and xe2x80x98SWTCHxe2x80x99 representing occurrence of inversion of xe2x80x98MPSxe2x80x99 value, in every ST. Thus, probability-state transition in coding processing is implemented in accordance with the above described probability transition table.
When xe2x80x98PIXxe2x80x99 is judged to be xe2x80x98MPSxe2x80x99 in STEP S200, xe2x80x98LSZxe2x80x99 is subtracted from value of xe2x80x98Axe2x80x99-register in the same manner as the case of xe2x80x98LPSxe2x80x99 (STEP S207). The value of xe2x80x98Axe2x80x99-register undergoing subtraction is compared with 0x8000 (xe2x80x980xxe2x80x99 indicating that xe2x80x980xxe2x80x99 is hexadecimal number) (STEP S208). When the result of the comparison is xe2x80x98Axe2x80x99xe2x89xa70x8000, no processing is implemented, thus coding processing of xe2x80x98PIXxe2x80x99 is terminated. When the result of the comparison is xe2x80x98Axe2x80x99 less than 0x8000, value of the xe2x80x98Axe2x80x99-register is compared with xe2x80x98LSZxe2x80x99 (STEP S209). When the result of comparison is xe2x80x98Axe2x80x99 less than xe2x80x98LSZxe2x80x99, addition between value of the xe2x80x98Cxe2x80x99-register and value of the xe2x80x98Axe2x80x99-register, and substitution of xe2x80x98LSZxe2x80x99 into xe2x80x98Axe2x80x99-register are implemented (STEP S210). Finally, substituting xe2x80x98NMPS[ST[CX]]xe2x80x99 into xe2x80x98ST[CX]xe2x80x99. The xe2x80x98NMPS[ST[CX]]xe2x80x99 is next objective of transition, after normalization processing (STEP S211), coding processing of xe2x80x98PIXxe2x80x99 is terminated.
FIG. 3 shows a flowchart of xe2x80x98normalization processingxe2x80x99. One bit of Left-shift of both of xe2x80x98Axe2x80x99-register and xe2x80x98Cxe2x80x99-register, and subtraction of xe2x80x98CTxe2x80x99-value are implemented (STEP S300). The subtraction processing of the above-described STEP S300 is continued up to A less than 0x8000, at the time when xe2x80x98Axe2x80x99 comes into xe2x80x98Axe2x80x99xe2x89xa70x8000 (STEP S309), the normalization processing is terminated.
When xe2x80x98CTxe2x80x99 comes into xe2x80x98CTxe2x80x99=0 during processing of the above described STEP S300 (STEP S301/Yes), it causes deterministic code part of the xe2x80x98Cxe2x80x99-register to be substituted into xe2x80x98TEMPxe2x80x99-register together with carry (STEP S302). Here, xe2x80x98Cxe2x80x99-register consists of 16 bits of operation-bit, 3 bits of carry propagation absorption-bit, 8 bits of code-bit generated, and one bit of carry-bit.
When value of the xe2x80x98TEMPxe2x80x99-register is xe2x80x98TEMPxe2x80x99-register=xe2x80x980xffxe2x80x99 (STEP S305), count-up of variable xe2x80x98SCxe2x80x99 is implemented (STEP S306). Further, when value of the xe2x80x98TEMPxe2x80x99-register is xe2x80x98TEMPxe2x80x99 less than xe2x80x980xffxe2x80x99 (STEP S305/No), previously stored data within the buffer is outputted as code, moreover, outputting xe2x80x980xffxe2x80x99 in number of xe2x80x98SCxe2x80x99 times (STEP S307). Subsequently, initialization of xe2x80x98SCxe2x80x99 is implemented to write value of current xe2x80x98TEMPxe2x80x99-register into the buffer (STEP S307).
In STEP S303, when value of the xe2x80x98TEMPxe2x80x99-register is xe2x80x98TEMPxe2x80x99 greater than xe2x80x980xffxe2x80x99, STEP S303 adds xe2x80x9c1xe2x80x9d to value of the buffer, subsequently, output of content of the buffer and xe2x80x98SCxe2x80x99-times output of xe2x80x9c0x00xe2x80x9d are implemented. Then, initialization of xe2x80x98SCxe2x80x99 and rewriting of xe2x80x98TEMPxe2x80x99-register are implemented (STEP S304). Here, only real code exception for carry-bit is written into the xe2x80x98TEMPxe2x80x99-register.
In STEP S308, xe2x80x98clearxe2x80x99 of high order bit of xe2x80x98Cxe2x80x99-register and xe2x80x98initializationxe2x80x99 of xe2x80x98CTxe2x80x99-value are implemented.
In the conventional image coding device disclosed in the Japanese Patent Application Laid-Open No. HEI 6-121172, and the Japanese Patent Application Laid-Open No. HEI 6-225158, these devices realize real time coding. Further, the Japanese Patent Application Laid-Open No. HEI 8-154059 discloses a coding device which implements coding/decoding in high speed.
However, in algorithm of arithmetic coding of the above-described conventional example, the content of the probability transition table should be read therein from the probability transition table for predicting respective pixels, further, rewrite and read-in of xe2x80x98STxe2x80x99 and xe2x80x98MPSxe2x80x99 should be implemented on that occasion in every respective xe2x80x98CTxe2x80x99. Generally, probability transition table is constituted by xe2x80x98ROMxe2x80x99. Prediction of xe2x80x98CXxe2x80x99 is implemented on xe2x80x98RAMxe2x80x99, thereby, several cycles are required for read and write thereof, thus taking times. Further, since several clocks of read/write cycles are required for coding one pixel, there occurs problem that processing is too late for image data which is inputted continuously in high speed. In recent years, concerning scanner device and so forth, image reading becomes high speed, thus image reading speed is high speed. For that reason, problem of processing speed becomes important problem.
Further, in the conventional image coding device which is disclosed in the Japanese Patent Application Laid-Open No. HEI 6-121171 and the Japanese Patent Application, there is no description concerning occurrence of xe2x80x98area widthxe2x80x99 (of value of LPZ) of less probability symbol xe2x80x98LPSxe2x80x99 for the probability presumption and xe2x80x98renewalxe2x80x99 of probability presumption information. Furthermore, when the device disclosed extracts deterministic code from the xe2x80x98Cxe2x80x99-register, since code size outputted therefrom is different caused by the number of shift or the value of xe2x80x98CTxe2x80x99, subsequent processing becomes complicated.
Also, in the Japanese Patent Application Laid-Open No. HEI 8-154059, there is no description concerning occurrence of xe2x80x98area widthxe2x80x99 (of value of xe2x80x98LPZxe2x80x99) of xe2x80x98LPSxe2x80x99 for the probability presumption and renewal of probability presumption information. Furthermore, in this place, the number of shift of the xe2x80x98Axe2x80x99-register is also used at the time of code outputting of xe2x80x98Cxe2x80x99-register. Therefore, it becomes necessary to allow overflow caused by shift, thus enlargement of bit-width is implemented.
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problem, to provide an image signal processing device comprising probability presumption information processing circuit capable of implementing coding/decoding processing without delay in relation to inputted data with constant speed while implementing renewal of probability presumption information.
According to a first aspect of the present invention, in order to achieve the above-mentioned object, there is provided an image signal processing device provided with a probability presumption information processing circuit which comprises a transition state renewal part for implementing maintenance/renewal of a status (xe2x80x98STxe2x80x99) value corresponding to respective contexts (xe2x80x98CXxe2x80x99) and a more probability symbol (xe2x80x98MPSxe2x80x99) value of the xe2x80x98CXxe2x80x99, an xe2x80x98Axe2x80x99-register operation part for implementing subtraction between value of an xe2x80x98Axe2x80x99-register and occurrence probability (xe2x80x98LSZxe2x80x99) of a less probability symbol (xe2x80x98LPSxe2x80x99) value, or shift of the xe2x80x98Axe2x80x99-register, a probability transition table for outputting corresponding the xe2x80x98LSZxe2x80x99, next objective of transition (xe2x80x98NMPSxe2x80x99) when coding candidate pixel value (xe2x80x98PIXxe2x80x99) is the xe2x80x98MPSxe2x80x99, next objective of transition (xe2x80x98NLPSxe2x80x99) when the xe2x80x98PIXxe2x80x99 is the xe2x80x98LPSxe2x80x99, and value of occurrence of inversion of the xe2x80x98MPSxe2x80x99 value (xe2x80x98SWTCHxe2x80x99), in answer to value of inputted the xe2x80x98STxe2x80x99, a flip-flop for adjusting timing of data, a xe2x80x98Cxe2x80x99-register operation part for implementing addition/subtraction between the xe2x80x98Cxe2x80x99-register and the xe2x80x98Axe2x80x99-register and/or shift of the xe2x80x98Cxe2x80x99-register, and a xe2x80x98CTxe2x80x99 renewal part for generating timing of input/output of signal.
According to a second aspect of the present invention, in the first aspect, there is provided an image signal processing device, wherein the probability presumption information processing circuit is capable of being applied to coding processing and/or decoding processing.
According to a third aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the probability presumption information processing circuit in coding processing further comprises a xe2x80x98PIXxe2x80x99 comparator for discriminating whether pixel (xe2x80x98PIXxe2x80x99) inputted therein is xe2x80x98MPSxe2x80x99 or xe2x80x98LPSxe2x80x99, and a code output part for extracting to be outputted a code from the xe2x80x98Cxe2x80x99-register.
According to a fourth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the probability presumption information processing circuit further comprises an xe2x80x98Axe2x80x99/xe2x80x98Cxe2x80x99 comparator for implementing comparison of value of the xe2x80x98Axe2x80x99-register with value within bit for operation in the xe2x80x98Cxe2x80x99-register, before determining whether the xe2x80x98PIXxe2x80x99 is the xe2x80x98MPSxe2x80x99 or the xe2x80x98LPSxe2x80x99.
According to a fifth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the transition state renewal part comprises a xe2x80x98CXxe2x80x99 decode circuit for implementing decode of xe2x80x98CXxe2x80x99 value, an xe2x80x98MPSxe2x80x99 inversion circuit for implementing inversion of xe2x80x98MPSxe2x80x99 in accordance with value of xe2x80x98SWTCHxe2x80x99, an xe2x80x98STxe2x80x99 renewal circuit for implementing output of xe2x80x98ST[CX]xe2x80x99 corresponding to the xe2x80x98CXxe2x80x99 inputted therein, and renewal of transition state of corresponding xe2x80x98CXxe2x80x99 for coding of next pixel, and an xe2x80x98MPSxe2x80x99 renewal circuit for implementing output of xe2x80x98MPS[CX]xe2x80x99 corresponding to xe2x80x98CXxe2x80x99 inputted therein and renewal of xe2x80x98MPSxe2x80x99 value of corresponding xe2x80x98CXxe2x80x99 for coding of next pixel.
According to a sixth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the transition state renewal part comprises a xe2x80x98CXxe2x80x99 decode circuit for implementing decode of xe2x80x98CXxe2x80x99 value, an xe2x80x98MPSxe2x80x99 inversion circuit for implementing inversion of xe2x80x98MPSxe2x80x99 in answer to value of xe2x80x98SWTCHxe2x80x99, a xe2x80x98PIXxe2x80x99 determination circuit for calculating pixel which is result of decoding, an xe2x80x98STxe2x80x99 renewal circuit for implementing output of xe2x80x98STxe2x80x99 value of xe2x80x98ST[CX]xe2x80x99 corresponding to xe2x80x98CXxe2x80x99 and renewal of state of corresponding xe2x80x98CXxe2x80x99 for coding of next pixel, an xe2x80x98MPSxe2x80x99 renewal circuit for implementing output of xe2x80x98MPSxe2x80x99 value of xe2x80x98MPS[CX]xe2x80x99 corresponding to xe2x80x98CXxe2x80x99 and renewal of xe2x80x98MPSxe2x80x99 value of corresponding xe2x80x98CXxe2x80x99 for coding of next pixel, and an exclusive NOR for configuring condition of xe2x80x98PIXxe2x80x99-determination, xe2x80x98MPSxe2x80x99-inversion, and state transition.
According to a seventh aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the xe2x80x98Axe2x80x99-register operation part comprises a flip-flop for implementing maintenance/renewal of value of xe2x80x98Axe2x80x99-register, an xe2x80x98Axe2x80x99-register subtraction control part for implementing control of subtraction of the xe2x80x98Axe2x80x99-register, an xe2x80x98Axe2x80x99-register comparison circuit for implementing comparison of value of xe2x80x98Axe2x80x99xe2x80x94xe2x80x98LSZxe2x80x99 with value of xe2x80x98LSZxe2x80x99, a shift quantity determination part for calculating shift quantity from value of the xe2x80x98Axe2x80x99-register inputted therein, and a shift circuit for implementing shift of the xe2x80x98Axe2x80x99-register in accordance with shift quantity outputted from the shift quantity determination part.
According to an eighth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the probability transition table comprises an xe2x80x98LSZxe2x80x99 selector for outputting value of xe2x80x98LSZxe2x80x99 corresponding to xe2x80x98STxe2x80x99 value inputted therein, an xe2x80x98NMPSxe2x80x99 selector for outputting value of xe2x80x98NMPSxe2x80x99 corresponding to xe2x80x98STxe2x80x99 value inputted therein, an xe2x80x98NLPSxe2x80x99 selector for outputting value of xe2x80x98NLPSxe2x80x99 corresponding to xe2x80x98STxe2x80x99 value inputted therein, and an xe2x80x98SWTCHxe2x80x99 selector for outputting value of xe2x80x98SWTCHxe2x80x99 corresponding to xe2x80x98STxe2x80x99 value inputted therein.
According to a ninth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the xe2x80x98Cxe2x80x99-register operation part comprises a flip-flop for implementing maintenance/renewal of value of the xe2x80x98Cxe2x80x99-register, an adder for implementing addition of value of the xe2x80x98Cxe2x80x99-register and value of the xe2x80x98Axe2x80x99-register, a selector for selecting whether it causes output of the adder to be used or it causes output of the flip-flop to be used directly as value of the xe2x80x98Cxe2x80x99-register, an exclusive OR for generating control signal of the selector, a shift circuit for implementing shift of the xe2x80x98Cxe2x80x99-register in accordance with shift quantity calculated by the xe2x80x98Axe2x80x99-register operation circuit, and a mask circuit for implementing xe2x80x9c0xe2x80x9d-clear of bit corresponding code-part outputted when code-output is generated.
According to a tenth aspect of the present invention, in the first or the second aspect, there is provided an image signal processing device, wherein the xe2x80x98CTxe2x80x99 renewal part comprises an adder for implementing addition of shift quantity calculated in the xe2x80x98Axe2x80x99-register operation part and xe2x80x98CTxe2x80x99 value outputted from the flip-flop, a flip-flop for implementing maintenance of xe2x80x98CTxe2x80x99 value, and a flip-flop for implementing adjustment of timing of output signal of the adder.
According to an eleventh aspect of the present invention, in the tenth aspect, there is provided an image signal processing device, wherein the code extraction part comprises a shift circuit for extracting code from the xe2x80x98Cxe2x80x99-register in accordance with xe2x80x98CTxe2x80x99 outputted from the xe2x80x98CTxe2x80x99 renewal part.
According to a twelfth aspect of the present invention, in the third aspect, there is provided an image signal processing device, wherein the xe2x80x98PIXxe2x80x99 comparator is constituted using an exclusive NOR gate circuit.
As stated above, the image signal processing device according to the invention realizes accumulation of the status data for probability transition and the probability transition table using the logical circuit. For that reason, high-speed cycle of read and write of above-described probability presumption information is implemented, with the result that processing speed of the whole coding processing is improved.
Further, with respect to bit-width of the xe2x80x98Cxe2x80x99-register for generating code, the image signal processing device causes bit-width of bit of xe2x80x98LSZxe2x80x99 to be equalized with bit-width of bit of definite code so that the maximum number of times of code output in coding of 1 pixel becomes 1 time. Furthermore, the image signal processing device employs the sum of shift quantity calculated in the xe2x80x98Axe2x80x99-register operation part and xe2x80x98CTxe2x80x99 value representing code accumulated status of the definite code bit of the xe2x80x98Cxe2x80x99-register as a signal for detecting code status at the time of code output from the xe2x80x98Cxe2x80x99-register. Due to this matter, it becomes possible to perform code output smoothly from the definite bit-position without enlarging bit-width of the xe2x80x98Cxe2x80x99-register excessively.
As described above, when the present invention is used, it becomes to implement coding processing without delay to the pixel inputted continuously, thus high speed coding processing with constant speed is capable of being realized. Further, similarly, also concerning the decoding, since it is capable of outputting image without delay while implementing decoding processing continuously, it becomes possible to realize high speed decoding processing with constant speed.
Moreover, according to the invention, renewal part of probability estimation information realized using device such as ROM and/or RAM until now can be realized using logical circuit. The logical circuit is applied to a coding device and/or a decoding device so that it is capable of being processed without delay to data inputted continuously in high speed. Further, the invention causes bit-width of definite code bit within the xe2x80x98Cxe2x80x99-register to be equalized with bit-width of bit for operation, namely bit-width of xe2x80x98LSZxe2x80x99 which is area-width of inferior symbol so as to cause the number of times of maximum code output in 1 time of processing to be 1 time, thus processing is capable of being performed smoothly to data inputted continuously.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.